Recently, to develop very high-density non-volatile semiconductor-memories for using in notebook computers mobile phones, and portable CD players and so on for replacing the conventional mass storage system draws much attention. One of attractive non-volatile memory is mask ROM (read only memory), which stores predetermined and commonly used information before the chip is encapsulated. Commonly used program or information includes an operating system (OS), a fixed subroutine program, and tables etc., as is stated in U.S. Pat. No. 4,744,054 to K. Kawata et al., issued on May 10, 1988. Generally, most of mask ROM is manufactured with the same basic structure, and be set the thresholds of the channel regions below the gate to the same predetermined value (e.g. 0.2-1 V) i.e. in the predetermined "on" state except those being programmed to "off" state transistor (by raising the thresholds of the MOS transistors). Hence, after receiving an order for a special program from customer, a mask ROM is produced to perform the programming, and to finish production; hence it gives a short turn around time.
Currently, the mask ROM with buried bit lines is one of the popular mask ROMs due to its small dimensions and high density. For examples, as is shown in FIG. 1, a conventional method of fabricating mask ROM in which a polysilicon layer 14 formed on gate insulating layer 13 as word lines, with implanted n+ region 16 as buried bit lines and then using contact holes for final metal interconnection. It is noted that there are many processes to be performed to complete the whole integrated circuit i.e. wafers will undergo several high temperature processes. Each high temperature processes could cause the out diffusion of impurities in area such as buried bit line, so that the spacing between two adjacent buried bit lines will become narrow, and it results in inducing cell punchthrough to occur. In addition, such a mask ROM would be with high resistance in the impurity region 16 (due to impurities out diffusion), and thus cause much difficult to fabricate a high-speed memory. Seung et al., in "U.S. Pat. No. 5,688,661 issued on Nov. 18, 1997," proposed an improved structure wherein a silicide 12 formed on the diffusion buried layer (BN+), and effectively reduces a sheet resistance of a bit line and a contact resistance of source/drain regions, as shown in FIG. 2.
Another method of fabricating a high density flat mask ROM with diffusion buried layer is reported by C. C. Hsue et al., in U.S. Pat. No. 5,668,031 issued on Sep., 16, 1997, as shown in FIG. 3. The dielectric layer 35 is formed at least partially between the source/rain electrode area 38 and the silicon substrate 30, thereby reducing leakage current. Since the structure with a dielectric layer to isolate the silicon substrate and source/rain electrodes and hence, the distance between adjacent source/drain electrodes can be minimized. However, the processes proposed by C. C. Hsue et al., are quite complicate, In processes, multiple steps are demanded to form polysilicon layer and refill the trench, at the same time the native oxide may formed between the interface of polysilicon layers. Furthermore, the feature sizes of mask ROMs are limited by the lithographic technology, hence whether it could apply to form very high-density mask ROM is not known.